The present invention relates to a Trellis decoder in a trellis coding modulation system, and more particularly to a Trellis decoder used especially in a QAM modulation/demodulation system for concurrently changing the amplitude and the phase.
In a multilevel QAM modulation/demodulation system, an error may occur in a signal after the QAM demodulation due to noise or reflection generated in a transmission path during signal transmission. Therefore, a transmission signal is subjected to coding for error correction for transmission at a transmitting side.
As for a multilevel QAM symbol in the multilevel QAM modulation/demodulation system, each symbol in the I axis and Q axis is expressed with an X bit such as xe2x80x9cIxxe2x88x921 Ixxe2x88x922 . . . Ixxe2x88x921 Ix0, Qxxe2x88x921 Qxxe2x88x922 . . . Qx1 Qx0xe2x80x9d (any of xe2x80x9cIxxe2x88x921xe2x80x9d, xe2x80x9cIxxe2x88x922xe2x80x9d, xe2x80x9cIx1xe2x80x9d, xe2x80x9cIx0xe2x80x9d, xe2x80x9cQxxe2x88x921xe2x80x9d, xe2x80x9cQxxe2x88x922xe2x80x9d, xe2x80x9cQx1xe2x80x9d and xe2x80x9cQx0xe2x80x9d is either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d). The transmitting side of the multilevel QAM modulation/demodulation system subjects a signal to multilevel QAM modulation and transmits the modulated signals by allocating data subjected to convolutional coding to xe2x80x9cIx0xe2x80x9d and xe2x80x9cQx0xe2x80x9d both of which are the least significant bits (described LSB hereinafter) in the multilevel QAM symbols and also allocating data not being subjected to convolutional coding to a part of high-order xe2x80x9cXxe2x88x921xe2x80x9d bits in the xe2x80x9cIxxe2x88x921xe2x80x9d to xe2x80x9cIx1xe2x80x9d bits and in the xe2x80x9cQxxe2x88x921xe2x80x9d to xe2x80x9cQx1xe2x80x9d bits excluding the LSBs in the symbols in the I axis and Q axis.
A receiving side subjects a received signal to multilevel QAM demodulation to obtain a demodulated signal, inputs the signal into a Trellis decoder and corrects an error therefor, and estimates a QAM symbol transmitted at the transmitting side. The demodulated signal in the I axis and Q axis is an N-bit soft decision signal respectively. A part of the high-order xe2x80x9cXxe2x80x9d bits in the signal represents an estimated value of the QAM symbol, and a part of the low-order xe2x80x9cNxe2x88x92Xxe2x80x9d bit excluding the part of high-order xe2x80x9cXxe2x80x9d bit represents an error from each of the QAM symbols in the I axis and Q axis respectively.
The Trellis decoder generally comprises a delay circuit of a Viterbi decoder, an area determining circuit or a RAM; a selection circuit; a convolutional coder; and a demapper. Error correction for each xe2x80x9cNxe2x88x92X+1xe2x80x9d bit in a demodulated signal corresponding to the LSB in each of the QAM symbols in the I axis and Q axis is executed in the Viterbi decoder. Error correction for a part of a high-order xe2x80x9cXxe2x88x921xe2x80x9d bit in each of the QAM symbols is executed by using each estimated value of the LSB in each of the QAM symbols obtained by re-coding a result of error correction with the Viterbi decoder by the convolutional coder. A sign of each part of the high-order xe2x80x9cXxe2x88x921xe2x80x9d bit in each of the QAM symbols is delayed in the delay circuit and inputted into the selection circuit. With the operation, phases between signs of the parts of high-order xe2x80x9cXxe2x88x921xe2x80x9d bits in the QAM symbols and estimated values of the LSBs in the QAM symbols are correlated in the selection circuit.
FIG. 8 is a simulated view showing a correlation between 64QAM modulated signals and QAM symbols in the I axis for explaining conventional type of error correction for QAM symbols. In FIG. 8, 64QAM symbols are expressed with xe2x80x9cI2 I1 I0xe2x80x9d, and demodulated signals Ir in the I axis are expressed with xe2x80x9cIr2 Ir1 Ir0 Ie3 Ie2 Ie1 Ie0xe2x80x9d, which are expressed with complement numbers of two. A correlation between 64QAM modulated signals and QAM symbols in the Q axis is the same as described above. It is assumed that, when the transmitting side sends a symbol A xe2x80x9c110xe2x80x9d (mark ♦ in FIG. 8) and the receiving side demodulates the symbol, an error occurs in the demodulated signal due to noise in the transmission path so that a demodulated signal B xe2x80x9c101xxxxxe2x80x9d (mark xc3x97 in FIG. 8) or a demodulated signal C xe2x80x9c111xxxxxe2x80x9d (mark +in FIG. 8) are obtained. The mark x in the signals represents either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
(1) Error Correction for Demodulated Signal B xe2x80x9c101xxxxxe2x80x9d
Even if a value obtained by re-coding a result of error correction by the Viterbi decoder with the convolutional coder is xe2x80x9c0xe2x80x9d, the high-order two bits in the demodulated signal are still xe2x80x9c10xe2x80x9d, and hence, the demodulated signal can not be corrected to the transmitted symbol A xe2x80x9c110xe2x80x9d. Therefore, when a demodulated signal is the demodulated signal B, the area determining circuit needs to output four bits of xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d in case where the LSBs in the QAM symbols are xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. The selection circuit corrects, when the LSB at the symbol point is xe2x80x9c0xe2x80x9d, an error for the high-order two bits in the demodulated signal by selecting output xe2x80x9c11xe2x80x9d from the area determining circuit.
(2) Error Correction for Demodulated Signal C xe2x80x9c111xxxxxe2x80x9d
Even if a value obtained by re-coding a result of error correction by the Viterbi decoder with the convolutional coder is either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, the high-order two bits in the demodulated signal are still xe2x80x9c11xe2x80x9d. Therefore, when a demodulated signal is the demodulated signal C, the area determining circuit needs to output four bits of xe2x80x9c11xe2x80x9d and xe2x80x9c11xe2x80x9d in case where the LSBs in the QAM symbols are xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d.
Description below provides a summary of results of output from the area determining circuit and selection circuit based on the conventional technology.
(1) When a demodulated signal is in a range from xe2x80x9c1000000xe2x80x9d to xe2x80x9c1010111xe2x80x9d (Area (1) in FIG. 8), the area determining circuit outputs xe2x80x9c10xe2x80x9d and xe2x80x9c10xe2x80x9d, and the selection circuit outputs xe2x80x9c10xe2x80x9d and xe2x80x9c10xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
(2) When a demodulated signal is in a range from xe2x80x9c1011000xe2x80x9d to xe2x80x9c1100111xe2x80x9d (Area (2) in FIG. 8), the area determining circuit outputs xe2x80x9c11xe2x80x9d and xe2x80x9c10xe2x80x9d, and the selection circuit outputs xe2x80x9c11xe2x80x9d and xe2x80x9c10xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
(3) When a demodulated signal is in a range from xe2x80x9c1101000xe2x80x9d to xe2x80x9c1110111xe2x80x9d (Area (3) in FIG. 8), the area determining circuit outputs xe2x80x9c11xe2x80x9d and xe2x80x9c11xe2x80x9d, and the selection circuit outputs xe2x80x9c11xe2x80x9d and xe2x80x9c11xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
(4) When a demodulated signal is in a range from xe2x80x9c1111000xe2x80x9d to xe2x80x9c1111111xe2x80x9d and from xe2x80x9c0000000xe2x80x9d to xe2x80x9c0000111xe2x80x9d (Area (4) in FIG. 8), the area determining circuit outputs xe2x80x9c00xe2x80x9d and xe2x80x9c11xe2x80x9d, and the selection circuit outputs xe2x80x9c00xe2x80x9d and xe2x80x9c11xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
(5) When a demodulated signal is in a range from xe2x80x9c0001000xe2x80x9d to xe2x80x9c0010111xe2x80x9d (Area (5) in FIG. 8), the area determining circuit outputs xe2x80x9c00xe2x80x9d and xe2x80x9c00xe2x80x9d, and the selection circuit outputs xe2x80x9c00xe2x80x9d and xe2x80x9c00xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
(6) When a demodulated signal is in a range from xe2x80x9c0011000xe2x80x9d to xe2x80x9c0100111xe2x80x9d (Area (6) in FIG. 8), the area determining circuit outputs xe2x80x9c00xe2x80x9d and xe2x80x9c00xe2x80x9d, and the selection circuit outputs xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
(7) When a demodulated signal is in a range from xe2x80x9c0101000xe2x80x9d to xe2x80x9c0111111xe2x80x9d (Area (7) in FIG. 8), the area determining circuit outputs xe2x80x9c01xe2x80x9d and xe2x80x9c01xe2x80x9d, and the selection circuit outputs xe2x80x9c01xe2x80x9d and xe2x80x9c01xe2x80x9d when the LSBs therein are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d respectively.
In the conventional type of Trellis decoder, however, when an error is to be corrected for a part of a high-order xe2x80x9cXxe2x88x921xe2x80x9d bit in a QAM symbol, xe2x80x9c(Xxe2x88x921)xc3x974xe2x80x9d bits in I and Q axis respectively, total xe2x80x9c(Xxe2x88x921)xc3x972xe2x80x9d bits, are required as an output from the area determining circuit.
Therefore, a size of a delay circuit of a RAM or the like into which output from the area determining circuit is inputted is xe2x80x9c(Xxe2x88x921)xc3x974 bitsxc3x97mxe2x80x9d. Herein m indicates a delay after a value at the xe2x80x9cNxe2x88x92X+1xe2x80x9d bit from the high order bit in the demodulated signal is inputted into a Trellis decoder until the value is re-coded. For example, in a case of 64QAM, the area determining circuit outputs a 4-bit sign for each of the axes as described above, so that a 8-bit sign as a total of the signs in the Q axis and I axis will be inputted into the delay circuit. Therefore, conventionally, a scale of a delay circuit has been xe2x80x9c8 bitsxc3x97m wordsxe2x80x9d.
The delay m depends on a length of truncation of a sign by a Viterbi decoder, and the length of truncation of a sign needs a length five to seven times as long as that of a convolutional code to be bound. Input to the delay circuit depends on a multilevel-number in a QAM symbol. All these facts indicate that the size of the delay circuit becomes bigger in association with a longer length of a convolutional code to be bound, and also becomes bigger in association with a larger multilevel-number in a QAM symbol, which makes the scale of the circuit of a Trellis decoder bigger.
It is an object of the present invention to obtain, for solving the problems described above, a Trellis decoder in which scale of the circuit as a whole is as small as possible through a step of decreasing a number of elements for a delay circuit as small as possible by reducing a number of input bits to the delay circuit as small as possible.
With the present invention, a pre-circuit outputs a sign expressed with X bits according to a sign in the high-order xe2x80x9cX+1xe2x80x9d-bit of a demodulated signal; an area determining circuit outputs a sign expressed with xe2x80x9cXxe2x88x921xe2x80x9d bits according to the X-bit sign outputted from the pre-circuit; and a delay circuit receives the xe2x80x9cXxe2x88x921-bit sign outputted from the area determining circuit and a sign for the most significant bit (described MSB hereinafter) in the demodulated signal and then delays a sign for the X bits as a total of the bits above and outputs the sign into a selection circuit. On the other hand, a Viterbi decoder corrects an error for a value of the LSB in a received symbol; a convolutional coder re-codes the value according to a result of error correction by the Viterbi decoder, obtains an estimated value of the LSB in the received symbol through the operation, and outputs the value to the selection circuit. The selection circuit receives a sign obtained by synchronizing the xe2x80x9cXxe2x88x921xe2x80x9d-bit sign from the area determining circuit as well as the sign for the MSB in the received symbol each outputted from the delay circuit and the estimated sign for the LSB in the received symbol outputted from the convolutional coder to each other, and identifies a value of a high-order xe2x80x9cXxe2x88x921xe2x80x9d-bit sign in the received symbol according to the signs.
With the present invention, a pre-circuit outputs a 3-bit sign according to a sign in the high-order 4-bit of the demodulated signal; an area determining circuit outputs a 2-bit sign according to the 3-bit sign outputted from the pre-circuit; and a delay circuit receives the 2-bit sign outputted from the area determining circuit and a sign for the MSB in the demodulated signal, delays a 3-bit sign as a total of the bits above, and outputs the sign to a selection circuit. On the other hand, a Viterbi decoder corrects an error for a value of the LSB in a received symbol; a convolutional coder re-codes the value according to a result of error correction by the Viterbi decoder, obtains an estimated value of the LSB in the received symbol through the operation, and outputs the value to the selection circuit. The selection circuit receives a sign obtained by synchronizing the 2-bit sign from the area determining circuit as well as the sign for the MSB in the received symbol each outputted from the delay circuit, and the estimated sign for the LSB in the received symbol outputted from the convolutional coder to each other, and identifies a value of a high-order 2-bit sign in the received symbol according to the signs.
With the present invention, a pre-circuit outputs a 3-bit sign according to a demodulated signal.
With the present invention, an area determining circuit outputs xe2x80x9c00xe2x80x9d when a demodulated signal is in arrange from xe2x80x9c0000000xe2x80x9d to xe2x80x9c0000111xe2x80x9d or from xe2x80x9c1111000xe2x80x9d to xe2x80x9c1111111xe2x80x9d, outputs xe2x80x9c01xe2x80x9d when a demodulated signal is in a range from xe2x80x9c0001000xe2x80x9d to xe2x80x9c0010111xe2x80x9d or from xe2x80x9c1101000xe2x80x9d to xe2x80x9c1110111xe2x80x9d, outputs xe2x80x9c10xe2x80x9d when a demodulated signal is in a range from xe2x80x9c0011000xe2x80x9d to xe2x80x9c0100111xe2x80x9d or from xe2x80x9c1011000xe2x80x9d to xe2x80x9c1100111xe2x80x9d and outputs xe2x80x9c11xe2x80x9d when a demodulated signal is in a range from xe2x80x9c0101000xe2x80x9d to xe2x80x9c1010111xe2x80x9d.
With the present invention, a selection circuit corrects an error for a value and identifies a high-order 2-bit sign in a received symbol according to the output from the area determining circuit, the MSB in the received symbol and the estimated sign for the LSB in the received symbol obtained through re-coding by the convolutional coder.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.